Demo 5.2: Half Adders, Full Adders and Carry
Everything designed so far has been a circuit that answers a question. Is this code valid BCD, should this segment be lit, is this combination the one we are watching for. The answers were true or false and nothing more was expected of them.
This one does arithmetic, and that changes what you can do as a designer. You no longer have to be told what the output should be, because you can work it out. If the circuit says 1 + 1 is 1 then the circuit is wrong, and no specification document is needed to settle it.
The subject is also, for the first time, unavoidably about time. A seven-segment decoder is seven independent functions and they all settle at once. An adder is a chain, and the top of a sum cannot be worked out until the bottom of it has been. That turns out to matter enormously, and the last part of this demonstration is about how much.
Carry, in one paragraph
Section titled “Carry, in one paragraph”Adding two bits has four cases and three of them are unremarkable: 0 + 0 is 0, 0 + 1 is 1, 1 + 0 is 1. The fourth is 1 + 1, which is 2, and 2 does not fit in one bit. In binary it is 10, so the answer needs a second output to hold the twos column. That second output is the carry, and every complication in this demonstration comes from it.
How to use it
Section titled “How to use it”The half adder gives you a four-row truth table and asks you to name the gate behind each output column before it will draw anything. There are six candidates and all six stay on offer. Wrong answers are explained by pointing at the row where they fail rather than simply being refused.
The full adder takes three bits instead of two and is shown twice: as two half adders with an OR gate, which is how it is built, and at gate level, which is what it reduces to. Toggle between them with the inputs untouched and the outputs do not move. There is also a panel that hides the truth table and asks you to fill in all eight rows yourself.
Four bits at once puts four full adders in a row. Set the two numbers with the bit toggles, or use the presets. Then press Watch the carry travel and step the carry along the chain by hand, which is the part worth slowing down for. The delay table underneath extrapolates what you have just watched out to 64 bits.
Half Adders, Full Adders and Carry
Arithmetic out of logic gates. Two bits, then three, then eight.
Walkthrough
Section titled “Walkthrough”Step 1: Name the two columns
Section titled “Step 1: Name the two columns”Open The half adder and look at the truth table before touching anything. Read the Sum column downwards, then the Carry column, and treat each as a two-variable function in its own right. This is the same move the seven-segment decoder turned on: a row tells you what the answer is, a column tells you what one output pin has to do.
The Carry column is the easier of the two. It is 0, 0, 0, 1, and the only row that needs a carry at all is the one where both bits are 1.
The Sum column is 0, 1, 1, 0, which is 1 when exactly one input is 1. If you pick wrongly you are told which row your gate fails on, which is more useful than being told no. Try OR deliberately: it is right for three rows out of four and wrong for the one that matters.
When both are named the schematic appears. Two gates, two shared input pins, and two outputs that have nothing to do with one another.
Step 2: Notice what a half adder cannot do
Section titled “Step 2: Notice what a half adder cannot do”Read the last paragraph on that tab. A half adder produces a carry but has no pin to receive one.
That is a real limitation and not a naming quirk. Try to imagine two of them side by side adding a two-bit number: the carry out of the right-hand one has nowhere to go. A half adder can only ever be the rightmost column of a sum, and every other column needs something with a third input.
Step 3: Watch the third input arrive
Section titled “Step 3: Watch the third input arrive”Open The full adder. It starts on the two half adder construction, which is worth reading as an assembly drawing rather than a circuit: both boxes are the part you just built, unchanged and unopened, and the only new component is the OR gate that collects the two carries.
Stop on the explanation of why an OR gate is enough. The two half adders can never both produce a carry, so the case that would distinguish OR from XOR cannot arise. That is a don’t-care condition, exactly like the six impossible BCD codes, arriving in a different disguise.
Then switch to Gate level with the inputs left alone. The gates change completely and the two output values do not move. One is the circuit as it is assembled, the other is the circuit as the truth table minimises, and both are the same function.
Step 4: Fill in the truth table yourself
Section titled “Step 4: Fill in the truth table yourself”Open Predict the outputs. The eight rows are there with the outputs hidden, and you are asked for the two output bits one row at a time. There is no logic to do: add the three input bits as ordinary numbers, write the total in binary using two bits, and the left-hand bit is the carry.
Finish all eight, then read the two output columns as patterns rather than as answers. Sum is 1 whenever an odd number of the three inputs is 1. Carry out is 1 whenever at least two of them are. Go back to the gate level view and those are precisely the two circuits on the sheet: a chain of XOR gates for the first, and a majority vote for the second.
Step 5: Put four of them in a row and then wait
Section titled “Step 5: Put four of them in a row and then wait”Open Four bits at once. The four stages each handle one column of the sum, and the wire in each gap is the whole idea: it is one wire with two names, called Cout at the right-hand end and Cin at the left-hand end, because it is an output of one stage and an input of the next.
Set the preset Ripple all the way, which is 7 + 1. Now press Watch the carry travel and step through it. Every stage has had its two operand bits since the beginning, and three of the four can do nothing at all with them, because a full adder with an invalid carry in produces nothing worth having. The chain resolves from right to left one stage at a time.
Try No carries at all and step through that too. Nothing has to travel, and the hardware waits exactly as long anyway. It cannot tell a carry that never happened from one that has not arrived yet.
Then set The largest it goes and look at the carry out. It is 1, the four sum bits read 15 when the answer is 31, and this adder has nowhere to put the missing bit. Whether that is a fault or a feature depends entirely on what is wired to that pin.
Step 6: Read the delay table
Section titled “Step 6: Read the delay table”The aside at the bottom is the reason the previous step was worth doing slowly.
Adding a stage to a ripple-carry adder adds to the length of the wait, because the new stage cannot start until the one below it has finished. The table follows that out to 64 bits, where the adder on its own would hold a clock down to about 128 MHz.
The escape is in the last paragraph and it comes straight back to the half adder from Step 1. For column i, the AND of the two bits says the column generates a carry no matter what arrives, and the XOR says it would propagate a carry that did arrive. Write those as G and P and every carry in the word can be expressed in terms of the operand bits alone, with no reference to the stage below, so they can all be computed at once. That is carry-lookahead, and the two gates it is built out of are the two gates you named in the first five minutes of this demonstration.
Check your understanding
Section titled “Check your understanding”Why is a half adder called half an adder?
A full adder is built from two half adders and an OR gate. Why is an OR gate sufficient to combine the two carries?
Match each part of an adder to what it is responsible for
You set a four-bit ripple-carry adder to compute 5 + 10, which produces no carry from any stage. How long does the result take to settle compared with 7 + 1, where a carry travels the whole chain?
A ripple-carry adder is extended from 4 bits to 64 bits. What happens to the worst-case settling time?
Wrap-up
Section titled “Wrap-up”Four things to take from this.
- Two bits cannot be added into one bit, so an adder has two outputs. Everything else follows from that one overflow.
- A full adder is a half adder problem solved twice. Recognising a part you already have inside a part you are about to build is most of what design work consists of.
- Two different-looking circuits can be the same function. The assembled version and the minimised version of the full adder produce identical outputs, and choosing between them is a matter of what you are optimising for.
- A chain of stages is a chain of waiting. The four-bit case hides it and the 64-bit case cannot, and the fix is to compute the carries from the operands rather than from each other.
The circuits here are still combinational: the outputs depend only on what the inputs are doing now, and given long enough they settle to one answer. Nothing in an adder remembers anything.
Next comes the rest of the standard combinational toolkit, and it is largely about routing rather than arithmetic. Decoders turn a binary code into one active line out of many, encoders do the reverse, and multiplexers and demultiplexers use those ideas to select one signal path out of several. Between them they are how a value gets from where it is to where it is needed, which is the other half of what a digital system spends its time doing.
© 2026 Derek Molloy, Dublin City University. All rights reserved.