Demo 6.5: Synchronous Counters, and the Price of Getting It Right
The last demonstration left a counter with a fault. Its four flip-flops were clocked in a chain, each by the one before it, so their outputs changed one after another rather than together. For a few tens of nanoseconds at every transition the four wires read a number that was not in the sequence: going from 7 to 8 it passed through 6, then 4, then 0.
The cause was one sentence long. The stages were working to different times. So the fix is to stop doing that, and Kuphaldt puts it as plainly as it can be put:
connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time
Do that and the ripple is gone, completely and at any speed, because there is no longer any ordering between the stages for a false state to hide in.
It also breaks the counter.
What the chain was quietly doing
Section titled “What the chain was quietly doing”In a ripple counter, a stage knew to toggle because it had just been clocked, and it had just been clocked because the stage below it had fallen. The wiring carried the information. Nobody had to work out whose turn it was, because the shape of the circuit answered the question.
Tie all the clocks together and that information is gone. Every flip-flop is now told the same thing at the same instant, and if all four are left in toggle mode then all four change at every edge. The result is 0000, 1111, 0000, 1111, which is a perfectly reliable divide-by-two on four wires at once and not a counter at all.
So something else must say which stages this edge is meant for. The rule is sitting in the count sequence, and Kuphaldt states it in one line:
just before a bit toggles, all preceding bits are “high”
Which is an AND of everything below it. It is also the carry from the demonstration on binary arithmetic: adding one flips the bottom bit always, and carries into the next bit only if that bit was already 1, and the carry keeps going for as long as it keeps meeting 1s. A counter is an adder that only ever adds one, and the AND chain is its carry chain.
How to use it
Section titled “How to use it”All clocked together shows the fix and the failure it causes. One button switches between every stage armed all the time, which does not count, and the gated version, which does. The rule is derived from the count table beside it.
The gating is the circuit: two AND gates, the enable lines drawn as waveforms next to the outputs, and stage boxes that turn amber a whole clock period before they toggle.
Up and down adds the second AND network from the Q̄ outputs, an OR per stage, and one control line to choose between them.
What it costs puts the delays back and compares the same 7 → 8 transition under both architectures, with the timing budget in nanoseconds.
Synchronous Counters, and the Price of Getting It Right
One clock for every flip-flop, the AND chain that decides whose turn it is, a control line that reverses the count, and where the speed limit went.
Walkthrough
Section titled “Walkthrough”Step 1: Break it first
Section titled “Step 1: Break it first”Open All clocked together with the J and K inputs set to All tied to 1, and press play.
The count reads 0, 15, 0, 15, and repeats. Every stage is armed at every edge, so every stage toggles at every edge, and the counter alternates between all zeros and all ones.
This is not a subtle failure and it is worth meeting head on, because it says exactly what the gating has to supply. The chain in the previous demonstration was doing real work, and taking it away has a cost that has to be paid somewhere.
Now press Gated by the rule and it counts 0 through 15 properly. Look at what has not changed: all four outputs still move on the same edge, at the same instant. The counting has been recovered without giving that up.
Step 2: Read the rule off the table
Section titled “Step 2: Read the rule off the table”Look at the table on the right, and specifically at the “which toggle” column against the binary column beside it.
- Q₀ is marked on every single row. It toggles every time, with no condition at all.
- Q₁ is marked on exactly the rows where Q₀ is 1.
- Q₂ is marked where Q₀ and Q₁ are both 1.
- Q₃ is marked where Q₀, Q₁ and Q₂ are all 1.
That is Kuphaldt’s rule, and notice that the enables are always a run of 1s from the bottom with no gaps. There is never a case where Q₂ is armed and Q₁ is not, because the condition for a stage contains the condition for the one below it.
That nesting is what makes the circuit cheap, and it is the subject of the next tab.
Step 3: Build it with two gates
Section titled “Step 3: Build it with two gates”Open The gating.
Because each condition contains the one below it, each stage can borrow the work already done:
| Stage | Condition | What it needs |
|---|---|---|
| FF₀ | always | J and K straight to logic 1 |
| FF₁ | Q₀ | one wire, no gate |
| FF₂ | E₁ · Q₁ | one two-input AND |
| FF₃ | E₂ · Q₂ | one two-input AND |
Four flip-flops and two gates. No wire runs further than one stage, and no gate has more than two inputs, which is what keeps this arrangement practical when the counter is sixteen bits wide instead of four.
Turn on the enable traces and step through. The thing to watch for is when an enable goes high: it rises a whole clock period before the toggle it authorises. The gates are deciding, from the outputs as they are now, what should happen at an edge that has not arrived yet. That margin is the entire timing budget of the circuit, and it is what the last tab is about.
Step to count 7. All three enables are high, all four stages are armed, and the next edge changes every bit at once. Step again and only E₀ is left.
Step 4: Reverse it with one wire
Section titled “Step 4: Reverse it with one wire”Open Up and down.
Kuphaldt’s down rule is the mirror image of the up rule: “all preceding bits are low prior to a toggle”. So the down network is the same AND chain reading Q̄ instead of Q, and nothing else about it changes at all.
The reason for the symmetry is worth having:
- Adding one carries into a bit when everything below it is 1, because the lower bits are about to run out and wrap.
- Subtracting one borrows from a bit when everything below it is 0, because the lower bits have nothing left to give.
Carry and borrow are the same idea from opposite ends, and 1s and 0s swap between them.
Build both chains, put an OR after each pair, and let one control line decide which is allowed through. U enables the up chain and U̅ enables the down chain, so exactly one term can ever reach the OR. Use the FF1/FF2/FF3 buttons to expand any stage’s selector and watch the two AND gates and the OR while you flip U.
Then flip U while it is running. It reverses from wherever it happens to be, which is the whole point.
Step 5: See what the fix actually bought
Section titled “Step 5: See what the fix actually bought”Open What it costs and slide the delay up from zero.
The two panels show the same 7 → 8 transition under the two architectures, with the same propagation delay applied to both, so the only difference is the wiring.
- The ripple counter passes through 6, 4 and 0, exactly as it did in the last demonstration.
- The synchronous counter goes straight from 7 to 8, at every setting of the slider.
There is no delay at which the synchronous counter produces a false state, because all four flip-flops are clocked by the same wire at the same instant and all four outputs change together one propagation delay later. There is no ordering, so there is no interval in which some have changed and others have not.
That is a stronger claim than “it is faster”. A ripple counter clocked slowly is still wrong for a few tens of nanoseconds at every transition. This one is never wrong at all.
Step 6: Find out where the limit went
Section titled “Step 6: Find out where the limit went”It did not disappear. It moved.
The gates have to finish deciding which stages to arm before the next edge arrives. If they have not, a flip-flop gets clocked while its J and K are still moving, and what it does then is not defined.
Three numbers, for 74LS parts:
- 20 ns from a clock edge until Q has settled
- 10 ns through one AND gate
- 20 ns of setup, meaning J and K must be stable that long before the edge
Add them for the four-bit chained version: 20 + (2 × 10) + 20 = 60 ns, so about 16.7 MHz. The ripple counter of the same width managed 12.5 MHz.
Now switch between Chained AND gates and One wide gate per stage and watch the table:
| Width | Ripple | Synchronous, chained | Synchronous, wide gates |
|---|---|---|---|
| 4 bits | 12.5 MHz | 16.7 MHz | 20.0 MHz |
| 8 bits | 6.25 MHz | 10.0 MHz | 20.0 MHz |
| 16 bits | 3.13 MHz | 5.56 MHz | 20.0 MHz |
The ripple counter loses a whole flip-flop delay per bit. The chained synchronous counter loses one gate delay per bit, which is half as bad. The wide-gate version does not lose anything at all, because the carry passes through a single gate however wide the counter is. The price is fan-in, since the top stage of a sixteen-bit counter would need a fifteen-input AND.
That trade is the counter’s version of the same choice adders make between ripple carry and carry lookahead, and it is the same trade every time: gates and fan-in bought against propagation delay.
Check your understanding
Section titled “Check your understanding”Four JK flip-flops have all their clock inputs tied to one clock, and all their J and K inputs tied to logic 1. What does this circuit do?
In a synchronous up-counter, what condition arms bit Q₃ to toggle at the next clock edge?
Why can a synchronous counter never show a false intermediate count, however fast it is clocked?
Match each item to what it is
A four-bit ripple counter and a four-bit synchronous counter are both built from 74LS parts and both clocked at 1 MHz, far below either one's limit. Which statements are true? Select all that apply.
Wrap-up
Section titled “Wrap-up”Five things to take away.
- Tie every clock input together and the ripple is gone, completely and at any speed, because there is no ordering left between the stages.
- That removes the information the chain was carrying. Every stage now hears the same thing at the same time, so gates must decide whose turn it is. Ungated, all four toggle at once and the thing does not count.
- The rule is the carry from binary addition: a bit toggles when all the bits below it are 1. Because each condition contains the one below it, four flip-flops need only two two-input AND gates.
- The down rule is the up rule with every input inverted, so a second chain from the Q̄ outputs, an OR per stage, and one control line give a counter that reverses on demand.
- The limit moved from the outputs to the inputs. There are no false states at any speed, but the gates must settle before the next edge: period > flip-flop delay + logic + setup. Around 16.7 MHz for a chained four-bit design, against 12.5 MHz for the ripple version, and the gap widens with every bit added.
Look at what this circuit actually is, with the counting set aside for a moment. It is a set of flip-flops holding a state, a block of combinational logic that looks at that state and works out the next one, and a clock that steps from one to the other. Nothing in that description mentions counting.
Replace the AND chain with different logic and the machine walks a different sequence. That is what the next demonstration does, and it does it by taking the logic away almost entirely: four flip-flops sharing a clock, with nothing between them, where the only decision left is what each D input is connected to. That one decision is enough to turn the same hardware into a store, into a shift register, or into a counter walking a sequence somebody chose rather than derived.
Choose the sequence deliberately, add inputs that change which way it goes, and you have a finite state machine, which is what a processor is made of and where this material is heading. The tools are already in your hands: a state table saying what follows what, and Karnaugh maps to turn it into gates.
A counter is that construction with the simplest sequence anyone could pick, which is why it is where the subject starts rather than where it ends.
© 2026 Derek Molloy, Dublin City University. All rights reserved.