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📝 Knowledge Test

Chapter 2 Knowledge Test

Section titled “Chapter 2 Knowledge Test”
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This section contains 20 interactive knowledge checks designed to test your understanding of the materials covered in Chapter 2. The questions span foundational edge computing concepts, state-of-the-art hardware, programming best practices, and distributed systems orchestration. The section includes some inheritance hierarchy questions to further help you digest the materials from Chapter 1.

Please remember that many of the quizzes have multiple correct answers, and you must select all applicable options to succeed. Take your time to carefully evaluate each option.

Good luck!

Derek.

Part 1: Core Concepts and Edge Constraints

Section titled “Part 1: Core Concepts and Edge Constraints”
Q1
Quiz
Select 0/3

Which of the following represent the primary drivers for transitioning computational tasks from the centralised cloud to the network edge?

Unlimited computational scalability by leveraging local area networks to permanently store and archive all historical raw data across the edge fleet.
Enhanced data privacy and security by processing sensitive biometric or industrial information locally, preventing exposure during transmission.
Reduced bandwidth consumption by filtering and analysing data at the source, transmitting only essential insights or model updates to the cloud.
Decreased latency for real-time decision-making, ensuring that immediate actions can be taken without unpredictable network delays.
Q2
Concept Match

Match the Edge AI Term to its Definition

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

TinyML
drag a definition here…
Model Drift
drag a definition here…
Catastrophic Forgetting
drag a definition here…
Offline-First Design
drag a definition here…

Definition Pool

The gradual decline in an AI model's accuracy because the real-world data distribution changes over time.
A scenario where a highly constrained model loses previously learned information while attempting to learn new data.
Engineering applications to gracefully handle extended periods of disconnection using local data caching and processing.
Enables machine learning inference directly on low-power microcontrollers, often consuming less than 1 milliwatt of power.
Q3
Quiz
Select 0/2

When distinguishing between the tiers of a modern edge computing architecture, which statements accurately describe their roles?

Endpoint devices are highly constrained sensors designed for ultra-low-power inferencing directly at the exact source of data generation.
Edge servers are ultra-low-power microcontrollers running on coin-cell batteries, deployed directly onto moving industrial machinery.
Endpoint devices serve as centralised data lakes that orchestrate long-term machine learning model training across the entire global network.
Edge servers act as intermediary nodes that aggregate data from multiple endpoints to handle heavier computational AI workloads locally.
Q4
Abstract Class Hierarchy

Build the Edge Architecture Hierarchy

Drag class names from the pool into the slots so each class sits below its parent in the inheritance tree. Abstract classes are shown in italics with an amber accent — slots expecting an abstract class are pre-marked with «abstract». Click Submit when you're done.

Inheritance Tree (base class on top)
«abstract»
«abstract»
·····
·····
«abstract»
·····

Available Classes

AnalyticsServer
PowerGrid
EndpointDevice
CloudNode
EdgeNode
SensorReading
NetworkCable
EdgeServer
SystemNode
DataPacket
Q5
Quiz
Select 0/1

Why is the volatility of SRAM a significant challenge for TinyML devices?

It generates excessive thermal heat, requiring microcontrollers to use active liquid cooling systems in industrial environments.
It requires the device to maintain a constant, high-bandwidth 5G connection to stream memory states to the cloud.
It permanently corrupts the pre-trained neural network weights stored in the flash memory during every read operation.
It means that any on-device training progress or dynamically learned state is completely lost upon a power-off or hardware reset.

Part 2: State-of-the-Art Hardware

Section titled “Part 2: State-of-the-Art Hardware”
Q6
Concept Match

Match the Hardware Architecture to its Strength

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

GPU
drag a definition here…
NPU
drag a definition here…
FPGA
drag a definition here…
ASIC
drag a definition here…

Definition Pool

A custom-made silicon chip offering a superior price-to-performance ratio and exceptional power efficiency for a fixed, specific workload.
A reprogrammable logic fabric offering unparalleled in-field reconfigurability and deterministic low-latency performance.
A dedicated co-processor specifically designed to accelerate matrix multiplication and tensor operations with high efficiency.
A parallel processing powerhouse highly effective for deep learning, computer vision, and generative AI workloads.
Q7
Quiz
Select 0/3

Which of the following characteristics accurately describe Neuromorphic Computing (such as Intel's Loihi 2)?

It relies entirely on synchronous, high-frequency clocking to guarantee the deterministic execution of massive, parallel deep neural networks.
It employs a highly efficient event-driven architecture that only activates processing when specific changes or spikes occur in the input data.
It operates asynchronously, mimicking the biological brain, which leads to unparalleled energy efficiency and low response latencies.
It integrates memory and processing directly into a single unified architecture, minimising the energy loss associated with constant data movement.
Q8
Abstract Class Hierarchy

Build the Processor Hierarchy

Drag class names from the pool into the slots so each class sits below its parent in the inheritance tree. Abstract classes are shown in italics with an amber accent — slots expecting an abstract class are pre-marked with «abstract». Click Submit when you're done.

Inheritance Tree (base class on top)
«abstract»
«abstract»
·····
«abstract»
·····
·····

Available Classes

SpecialisedAccelerator
NeuromorphicChip
SiliconWafer
Processor
NeuralProcessingUnit
Microcontroller
CoolingFan
ClockSignal
Motherboard
GeneralPurposeCPU
Q9
Quiz
Select 0/2

Regarding the ESP32 family of microcontrollers, which statements are true?

The ESP32-H2 is designed specifically to run full desktop operating systems like Windows 11 due to its high base clock speeds.
The ESP32 Classic relies exclusively on a powerful GPU architecture to render complex 3D graphics for embedded touch displays.
The ESP32-S3 features advanced vector processing extensions that significantly accelerate the integer arithmetic used in AI inference.
The ESP32-C3 utilises an open-source RISC-V core and serves as a highly cost-effective, single-core alternative for simple IoT nodes.
Q10
Concept Match

Match the AI Model Optimisation Technique

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

Quantisation
drag a definition here…
Pruning
drag a definition here…
Knowledge Distillation
drag a definition here…
Fine-tuning
drag a definition here…

Definition Pool

Reducing the mathematical precision of weights and activations (e.g., from 32-bit float to 8-bit integer) to save memory.
A critical recovery step applied after compression to retrain the model and recover any lost predictive accuracy.
Systematically identifying and removing unnecessary neurons or connections to create a sparser, faster network.
Training a compact 'student' model to emulate the output behaviour of a massive, complex 'teacher' model.

Part 3: Programming Best Practices

Section titled “Part 3: Programming Best Practices”
Q11
Quiz
Select 0/2

How does the adoption of 'DevSecOps' and the 'shift left' approach improve embedded software development?

Security penetration testing is exclusively delayed until the final deployment phase to avoid interrupting the initial software development sprints.
The 'shift left' approach ensures that software testing, validation, and security considerations are incorporated much earlier in the development lifecycle.
The Waterfall methodology is strictly enforced to ensure that all system requirements are permanently frozen before any coding or testing begins.
DevSecOps integrates development, security, and operations, promoting automation and collaboration across edge and cloud environments.
Q12
Class Hierarchy

Build the Operating Environment Hierarchy

Drag class names from the pool into the slots so each class sits below its parent in the inheritance tree, then click Submit.

Inheritance Tree (base class on top)
·····
·····
·····
·····
·····

Available Classes

EmbeddedLinux
BareMetal
BinaryExecutable
JTAGDebugger
FileSystem
RTOS
OperatingEnvironment
Compiler
ManagedOS
Q13
Quiz
Select 0/2

Which of the following are recommended best practices for Memory and Power Management in edge systems?

Dynamic Voltage and Frequency Scaling (DVFS) adjusts the processor's voltage and clock speed dynamically based on the current workload.
Event-driven processing ensures the CPU runs continuously at maximum frequency to guarantee that no rapid sensor events are missed.
Using pre-allocated memory pools with robust failsafes provides operational flexibility while maintaining strict determinism and preventing crashes.
Developers should rely entirely on dynamic memory allocation (malloc/new) throughout runtime to ensure maximum memory flexibility.
Q14
Concept Match

Match the Embedded Engineering Tool

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

RTOS
drag a definition here…
DMA
drag a definition here…
HIL Simulation
drag a definition here…
JTAG
drag a definition here…

Definition Pool

Validating firmware logic by running it against a simulated or physical hardware environment in real-time.
A hardware feature allowing peripherals to transfer data directly to memory without continuous CPU intervention.
A standard hardware interface used for low-level in-circuit debugging, boundary scanning, and memory inspection.
An operating system that guarantees deterministic, predictable timing for critical task execution.
Q15
Quiz
Select 0/2

Which strategies align with the principle of 'Security by Design' in embedded edge systems?

Transmitting all biometric sensor data in plain text to significantly reduce the computational overhead and power draw of encryption algorithms.
Implementing secure boot mechanisms to ensure that only cryptographically signed and trusted firmware can be executed by the hardware.
Enforcing the principle of 'keeping the edges dumb' by limiting sensitive data storage and processing it in highly secure server environments.
Disabling all forms of over-the-air (OTA) updates permanently to ensure that malicious actors cannot remotely modify the firmware after deployment.

Part 4: Distributed Programming and Orchestration

Section titled “Part 4: Distributed Programming and Orchestration”
Q16
Quiz
Select 0/2

What makes Federated Learning (FL) a transformative approach for distributed AI on edge devices?

It is exclusively used for wired industrial automation protocols and is legally prohibited from being applied to privacy-sensitive healthcare applications.
It mandates that all edge devices continuously upload their complete, raw datasets to a central cloud server to guarantee absolute model accuracy.
It enables collaborative machine learning model training without compromising local data privacy by keeping sensitive raw data strictly on-device.
It involves iterative cycles where local model updates (weight and parameter changes) are sent to a central server for aggregation into an improved global model.
Q17
Abstract Class Hierarchy

Build the Communication Protocol Hierarchy

Drag class names from the pool into the slots so each class sits below its parent in the inheritance tree. Abstract classes are shown in italics with an amber accent — slots expecting an abstract class are pre-marked with «abstract». Click Submit when you're done.

Inheritance Tree (base class on top)
«abstract»
«abstract»
·····
·····
«abstract»
·····

Available Classes

Matter
BaudRate
FrequencyBand
NetworkProtocol
EthernetCable
MQTT
Thread
MessagingProtocol
WirelessStandard
Antenna
Q18
Concept Match

Match the Distributed Orchestration Concept

Drag each definition into its matching concept slot, then click Submit. Tap × to return a placed card to the pool.

MQTT
drag a definition here…
Matter
drag a definition here…
K3s
drag a definition here…
WebAssembly (Wasm)
drag a definition here…

Definition Pool

A unifying application-layer standard that ensures seamless interoperability between IoT devices from different manufacturers.
A secure, platform-independent sandbox offering near-native execution speeds with a significantly smaller footprint than traditional containers.
A lightweight publish/subscribe messaging protocol designed for reliable communication in low-bandwidth IoT environments.
A highly simplified, lightweight Kubernetes distribution explicitly optimised for managing containers on constrained edge devices.
Q19
Quiz
Select 0/2

In the context of workload orchestration, what are the distinct advantages of K3s and WebAssembly (Wasm) at the edge?

WebAssembly (Wasm) offers a highly secure sandbox for executing 'serverless' edge functions, making it ideal for ultra-constrained nodes where even K3s is too heavy.
K3s provides a fully compliant Kubernetes cluster distributed as a single binary, radically reducing the memory footprint and CPU overhead required for orchestration.
Both K3s and WebAssembly require massive, liquid-cooled data centre infrastructure, meaning they are strictly deployed in the central cloud, never the edge.
Service Mesh technologies are used to physically wire K3s and Wasm nodes together using proprietary industrial Ethernet cables for maximum throughput.
Q20
Abstract Class Hierarchy

Build the Optimisation Strategy Hierarchy

Drag class names from the pool into the slots so each class sits below its parent in the inheritance tree. Abstract classes are shown in italics with an amber accent — slots expecting an abstract class are pre-marked with «abstract». Click Submit when you're done.

Inheritance Tree (base class on top)
«abstract»
«abstract»
·····
·····
«abstract»
·····

Available Classes

ArchitectureChange
OptimisationStrategy
Pruning
Overclocking
LiquidCooling
KnowledgeDistillation
SRAM
SizeReduction
Quantisation
DeepLearning

Congratulations on completing the Chapter 2 Knowledge Test! Review any questions you missed to ensure a solid foundation in hardware architectures and edge constraints before diving into the programming tutorials.

© 2026 Derek Molloy, Dublin City University. All rights reserved.