Demo 6.4: Asynchronous Counters, and Why They Ripple

The last demonstration left two facts sitting next to each other, waiting to be put together.

The columns of a four-bit binary count are square waves at halving frequencies: the least significant runs at half the clock, then a quarter, then an eighth, then a sixteenth. And a JK flip-flop with both inputs tied high halves the frequency of whatever is on its clock input.

So chain four of them. The clock drives the first, the first drives the second, the second drives the third. Each stage halves again, the four outputs come out at a half, a quarter, an eighth and a sixteenth, and those are exactly the four columns.

Four flip-flops, no gates, no arithmetic. It is the cheapest counter there is, and it is wrong in two separate ways that are both worth knowing about.

The one sentence this rests on

Look at a count sequence and ask not how often each bit changes, but when:

   0011
   0100   <- Q2 changed. So did Q1 and Q0, and they went 1 -> 0.
   0101
   0110   <- Q1 changed. Q0 went 1 -> 0.
   0111
   1000   <- Q3 changed. Q2, Q1 and Q0 all went 1 -> 0.

In an up-count, a bit toggles when the bit below it goes from 1 to 0. That is a falling edge on the lower bit’s Q, and it is the entire specification of the circuit. Everything on the first two tabs is a consequence of getting that one edge right or wrong.

How to use it

The chain wires it the obvious way and lets you watch the cascade travel along it: a clock edge lands on the first stage, and if that stage produces the right kind of edge, the next one goes too. Idealised, with no propagation delay.

Making it count up exposes two independent switches, the edge that stages 1 to 3 trigger on and whether they are clocked from Q or Q̄. Four combinations, and two of them count up.

What the delays do puts the delay back, on a slider that starts at zero. The ideal picture turns continuously into the real one.

Asynchronous Counters, and Why They Ripple

Four dividers in a chain, the two ways to stop it counting backwards, and the propagation delay that gives the arrangement its name.

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Chain four dividers together and you have a counter. Almost.

The previous demonstration left two facts on the table: the columns of a binary count are square waves at halving frequencies, and a JK flip-flop in toggle mode halves a frequency.
So chain four of them. The clock drives the first, the first drives the second, and so on down the line.
Each stage is a divide by two, so the four outputs run at a half, a quarter, an eighth and a sixteenth of the clock. Those are exactly the four columns.
There is no gating here and no shared clock. Each flip-flop is clocked by the one before it, which is what the word asynchronous means.
Watch the highlighting as it runs: a clock edge lands on the first stage, and if that stage produces the right kind of edge, the second one goes too, and sometimes the third and fourth after it.
Then read the count underneath, because something is wrong with it.

Animation speed1.50 clocks/s

t = 0.00 of 16

The obvious wiring: four positive-edge flip-flops, each clocked from the Q before it

The amber marks are the clock's rising edges, which is what stage 0 is triggered by. Every output is a clean square wave at half the frequency of the one above it, exactly as the count table demands.

Every waveform is right, and the count is backwards

Read the sequence off: it goes 15, 14, 13, 12, 11, 10, and carries on falling.
Nothing is broken. Each stage really is dividing by two, and each output really is half the frequency of the one before it, so all four waveforms have the shapes the count table requires.
What is wrong is the phase. The bits are the right shapes in the wrong relationship, and read together they spell the sequence backwards.
Here is the reason, and it is one sentence. In an up-count, a bit toggles when the bit below it goes from 1 to 0.
That is a falling edge on the lower bit's Q. These flip-flops fire on the rising one, which is the rule for counting down.
So the obvious wiring gives a perfectly good down-counter, and the next tab is about the two separate ways to turn it round.

What it actually counts0

clock	Q₃Q₂Q₁Q₀	count
0	1111	15
1	1110	14
2	1101	13
3	1100	12
4	1011	11
5	1010	10
6	1001	9
7	1000	8
8	0111	7
9	0110	6
10	0101	5
11	0100	4
12	0011	3
13	0010	2
14	0001	1
15	0000	0

Following the cascade

Step one clock at a time and watch which stages light up at each edge.
Most edges light only the first stage: its output changes, and the change is the wrong kind of edge to disturb anybody else.
Some edges light two stages, some light three, and one in every eight lights all four.
The pattern is not random. A stage fires only when every stage below it has produced the triggering edge, which happens on every second clock, then every fourth, then every eighth.
That is the same "each bit is half the frequency of the last" fact, seen as an event rather than as a waveform.

Why this is called asynchronous

There is one clock signal in this circuit and it reaches exactly one flip-flop.
Every other stage is clocked by its neighbour, so the stages are not working to a common time reference. They are passing a message along a line.
That is the definition of asynchronous, and it is also the definition of the fault on the third tab.
The alternative, where every flip-flop shares the one clock and gating decides which ones should toggle, is the synchronous counter and it is the next demonstration.
It is worth noticing how little hardware this version needs: four flip-flops and no gates at all. That cheapness is why it survives.

Walkthrough

Step 1: Follow the cascade

Open The chain and step it one clock at a time rather than letting it run.

Most clock edges light up only the first stage. Its output changes, and that change is the wrong kind of edge to disturb anybody else. Every second edge lights two stages. Every fourth lights three. One edge in every eight lights all four.

That pattern is not a coincidence and it is not random: a stage fires only when every stage below it has produced its triggering edge. It is the “each bit is half the frequency of the last” fact from the previous demonstration, seen as an event rather than as a waveform.

Now look at the waveforms. Every output is a clean square wave at exactly half the frequency of the one above it. All four shapes are precisely what the count table requires.

Step 2: Read the count, and discover it is backwards

Now read the numbers written underneath the waveforms, or the table beside them.

It counts 15, 14, 13, 12, 11, 10, 9, 8, and keeps falling.

Nothing is broken. Each stage really is dividing by two and each output really is half the frequency of the one before it. What is wrong is the phase: the bits are the right shapes in the wrong relationship, and read together they spell the sequence backwards.

The reason is the sentence from the top of this page. An up-count needs each bit to toggle when the bit below goes 1 → 0, which is a falling edge. These flip-flops are positive-edge triggered, so they fire on the 0 → 1 rising edge instead, and that is the rule for counting down.

Kuphaldt’s two-bit version of the same circuit does exactly this: the sequence runs “from 11 to 10 to 01 to 00 and back again to 11.”

Step 3: Turn it round, twice

Open Making it count up. It opens on the obvious wiring, still counting down.

Change only the edge to falling. The count turns round, and bubbles appear on the clock inputs of stages 1 to 3 in the schematic. This is Kuphaldt’s first fix: “If we used flip-flops with negative-edge triggering (bubble symbols on the clock inputs), we could simply connect the clock input of each flip-flop to the Q output of the flip-flop before it.”

Now put the edge back to rising and change only the source to Q̄. It counts up again, by a completely different route, and the links in the schematic now come off the bottom of each stage. This is what Kuphaldt calls “a less obvious solution”: Q̄ rises at exactly the instant Q falls, so a positive-edge flip-flop watching Q̄ sees the same event as a negative-edge flip-flop watching Q.

Finally set both. It counts down again, because you have made the same correction twice and it has cancelled.

Edge	Clocked from	Fires when the bit below	Counts
rising	Q	goes 0 → 1	DOWN
falling	Q	goes 1 → 0	UP
rising	Q̄	goes 1 → 0	UP
falling	Q̄	goes 0 → 1	DOWN

The third column is the whole table. Both switches invert the condition, so either one alone turns the counter round and both together cancel.

Step 4: Notice that down-counting is a feature

Two of the four combinations count down, and it is worth being clear that they are not broken.

A down-counter is a perfectly good circuit. A timer that counts down to zero and raises a flag is the shape of a great many designs, and if you wanted one, the table above tells you how to wire it.

The synchronous counter in the next demonstration has an up/down control, which is precisely this choice made switchable instead of soldered. Meeting it here, as a wiring decision with a clear rule behind it, makes that control obvious rather than magical when it arrives.

Step 5: Admit that nothing is instantaneous

Open What the delays do and put the slider at zero first.

At zero delay this is exactly the picture from the first two tabs: every transition goes straight from one count to the next, and the table of transitions says clean all the way down. That picture is a fiction. No flip-flop responds instantly; a 74LS76 takes about 20 ns from clock edge to settled output.

Now slide the delay up slowly and watch the pink stripes appear.

Each stage is clocked by the one before it, so the second cannot start until the first has finished, and the fourth waits for all three. The outputs therefore do not change together. They change in order, from the least significant end upwards, and the whole chain takes four delays to settle.

While that is happening, the four outputs are showing a number. It is a real number, present on real wires, and it is not part of the count sequence.

Step 6: Look at the worst transition

Press the 7 → 8 button on the close-up.

This is Kuphaldt’s example, and the demonstration reproduces it exactly:

   0111  ->  0110  ->  0100  ->  0000  ->  1000
     7        6        4        0        8

Q0 falls first, giving 6. That fall clocks Q1, which falls, giving 4. That clocks Q2, which falls, giving 0. That finally clocks Q3, which rises, giving 8. Four delays, three false states, and every one of them appears on the outputs.

Work along the transition table on the right and the pattern is clean: the number of false states at a transition is the number of bits that have to change, less one. The worst cases are 7 → 8 and 15 → 0, where all four bits move and three false values appear.

The counter is not wrong afterwards. It arrives at the right answer every single time. It is only wrong in between, which is fine if nothing reads it in between, and a serious fault if something does.

Step 7: Decide what to do about it

Two honest answers, and the demonstration gives both.

Live with it. If nothing reads the outputs except a human looking at LEDs, the ripple is invisible. If the counter is being used purely as a frequency divider then only one output matters and the rest can ripple as much as they like, which is by far the commonest use of these, and the reason the arrangement survives despite the fault. Clock it slowly enough and the false states are over long before anything looks.

Strobe it. Kuphaldt’s answer: give whatever reads the counter an enable input and hold it inactive while the ripple is happening. The same clock that drives the counter can generate that enable, because the ripple always begins at a known edge. The outputs still go wrong; nothing is allowed to look while they are.

That second answer works, and it means every reader of the counter needs an extra input and an extra wire. At which point it is worth asking whether the counter should simply not do this in the first place.

Check your understanding

Quiz

Select 0/1

Four positive-edge triggered JK flip-flops are chained, each clocked from the Q output of the one before it, all with J and K tied high. What does this circuit do?

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Quiz

Select 0/1

Kuphaldt gives a 'less obvious solution' for building an up-counter from positive-edge triggered flip-flops. What is it?

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Quiz

Select 0/1

A four-bit ripple counter goes from 7 to 8. Which values appear on its outputs during the transition, and why?

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Concept Match

Match each item to what it is

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Quiz

Select 0/4

Which of these are true of a four-bit ripple counter with realistic propagation delays? Select all that apply.

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Wrap-up

Five things to take away.

A ripple counter is four dividers in a chain, and it needs no gates at all. That cheapness is why it exists.
The obvious wiring counts backwards. An up-count needs each bit to toggle on the falling edge of the bit below, and positive-edge flip-flops clocked from Q fire on the rising one.
There are two independent fixes, negative-edge triggering from Q, or positive-edge triggering from Q̄, and doing both cancels. Down-counting is a mode, not a mistake.
The outputs do not change together. Each stage waits for the one before, so the count ripples up the chain and passes through values that were never in the sequence: 7 → 6 → 4 → 0 → 8.
The settling time adds up along the chain, which puts a hard ceiling on the clock, around 12.5 MHz for four 74LS76 stages, and lower with every bit you add.

The fault has a single cause: each stage is clocked by its neighbour, so the stages are working to different times. The fix is to stop doing that.

Connect every clock input to the same clock signal and all four flip-flops are triggered at the same instant, so all four outputs change together, one propagation delay later. One delay instead of four, no ordering between the stages, and therefore no intermediate values to be caught.

The cost is that something must now decide which stages should toggle at each edge, because they can no longer work it out from one another. The rule turns out to be as simple as the one at the top of this page: a bit toggles when all the bits below it are 1. That is an AND gate per stage, and it is the synchronous counter of the next demonstration.