Demo 6.2: Flip-Flops
The previous demonstration ended with a working store and one complaint. A D latch takes one input, has no combination that must be avoided, and holds a bit for as long as you like. The trouble was what it does while it is listening: it is transparent, so its output follows its input for the whole time the enable is high, and anything reading that output during the window reads whatever the input happened to be doing at that instant rather than a settled value.
The obvious response is to make the window shorter. Hold the enable high for less time, and less can go wrong inside it.
Follow that thought to the end and you arrive somewhere strange. The ideal window has no width at all, and a window with no width cannot be made from a signal you control, because your finger, your switch and your clock generator are all far too slow. What you need is a circuit that produces a window shorter than anything you could ask for by hand, and it turns out there is a source of very short intervals sitting in every circuit in this module, one that has been treated as a nuisance up to now.
Delay stops being the enemy
Section titled “Delay stops being the enemy”Every gate takes time. A signal arriving at an input does not appear at the output until a propagation delay has passed, and that fact has caused nothing but difficulty so far: it is why the ripple-carry adder is slow, it is why a decoder briefly shows an output that belongs to no valid input, and it is why two signals that ought to change together do not.
This demonstration uses it deliberately.
Take one signal and send it to a gate by two different routes, one direct and one through a few inverters. The two copies are the same signal, so most of the time the gate sees a consistent pair of values. But for a brief moment after every transition the direct copy has already changed and the delayed copy has not, and during that moment the gate is looking at the new value and the old value at the same time. Choose the gate correctly and it produces an output for exactly that long.
The width of that output is not something you set. It is the delay of the inverter chain, measured in nanoseconds, and it stays the same whether the clock pulse that produced it was a microsecond long or a second long. That is the window we could not build by hand.
How to use it
Section titled “How to use it”Edge triggering is the pulse detector on its own, and every conductor in it shows the level it is carrying. Choose the polarity, choose how many inverters are in the chain, and move the time cursor to read the circuit at any instant. The two arrows beside the slider step time on and back by exactly one gate delay, which is one stage of the chain, so a change can be walked along it one gate at a time. Values drawn in amber are the ones that have not caught up with the input yet, and the output goes amber for the same reason, since the gate producing it is no faster than the ones in front of it. The Jump inside the next pulse button parks the cursor just after an edge, and changing the number of inverters changes the pulse width while nothing else moves.
SR flip-flop is the gated SR latch with that pulse driving its enable. Use Clock up to deliver an edge, and Step to walk through what happens in four stages. All three flip-flop drawings carry the level on every conductor, in the colour that conductor is drawn in, and the pulse detector says in words whether it has just been triggered or is still waiting.
D flip-flop is the D latch with the same treatment, and its timing diagram carries a plain D latch on the bottom row for comparison.
JK flip-flop feeds the outputs back into the steering gates, which turns the input combination that was not allowed into the most useful one of the four.
Flip-flops: edge triggering, SR, D and JK
A window so short that nothing can move inside it, and the three flip-flops built on that idea.
Walkthrough
Section titled “Walkthrough”Step 1: Find the pulse
Section titled “Step 1: Find the pulse”Open the first tab and read it before touching anything.
The input is a single long pulse, eight time slots wide, and the amber line is sitting one gate delay past its rising edge. Every conductor in the drawing carries its level, so this can be read rather than imagined. Look at the two inputs of the AND gate. The one coming straight from the input is 1, because the input has already risen. The one arriving from the end of the inverter chain is also 1, because the chain is still showing what the input was doing three gate delays ago, and three inversions of a 0 is a 1.
Both inputs are 1, and the output is 1. The line under the output says it is one gate delay behind its inputs, which is worth holding on to for the next step: the AND gate is a gate, so it is no quicker to make up its mind than the inverters are.
Now look at the values inside the chain, because that is where the answer actually lives. Some are drawn in amber. Those are the nodes that have not caught up yet: they are still carrying what the input used to be, and the boundary between the settled values and the amber ones is the change itself, part way along the chain.
Step 2: Walk the change along, one gate at a time
Section titled “Step 2: Walk the change along, one gate at a time”Press the forward arrow beside the slider. Each press moves time on by exactly one gate delay, which is exactly one stage of the chain.
Watch two things together on each press. One more node loses its amber, because the change has reached it. And the count under the slider goes up.
Keep pressing. On the step where the count reaches three, the last amber value in the chain disappears, the delayed copy has caught up with the direct one, and the two inputs of the AND gate stop disagreeing. As far as its inputs are concerned the pulse is over at that moment. The output is still 1.
Press once more and it falls. That last step is the gate answering its own inputs, one propagation delay after they changed, and it is the same delay that put the leading edge of the pulse where it is. Step back onto the edge itself with the back arrow and you can see the other end of the same effect: both inputs are already high, the output chip has gone amber, and it reads 0, because no time has yet passed for the gate. Nothing in this circuit is instantaneous, and the final gate is not an exception to that.
So the pulse begins one gate delay after the edge and ends one gate delay after the chain settles. Both of its ends are late by the same amount, which moves the pulse without changing its width.
Nothing was switched off at either end. The change simply finished travelling down the chain, and the gate stopped seeing a disagreement a moment later. The pulse existed because the circuit was briefly holding stale information, and you can count the gates that were holding it.
The back arrow reverses the whole sequence, which is worth doing at least once: watch the amber values reappear one at a time from the far end of the chain.
Step 3: Prove that the width is the delay
Section titled “Step 3: Prove that the width is the delay”Switch between one, three and five inverters, keeping an eye on the width of the output pulse.
Each inverter you add makes the pulse one gate delay wider, and the relationship is exact rather than approximate: with five inverters the output is high for five readings of the counter, with three it is high for three, and with one it is high for one. Now try the A few clock cycles preset, where the input is high for only two slots at a time rather than eight. The output pulses are exactly the same width as before.
This is worth pausing on, because it is the property that everything else depends on. The width of the pulse has nothing to do with the shape of the clock. It is a fact about the silicon the gates were made from, and that is why a flip-flop responds to an edge rather than to a level: the edge is the only part of the clock the detector can see.
Step 4: Turn it over
Section titled “Step 4: Turn it over”Switch to Falling edge, NOR.
Only one gate has changed. The inverter chain is identical, and the AND gate at the end has become a NOR gate. Just after a falling edge the direct copy is low and the delayed copy is still low, so a NOR gate produces 1 for the same brief interval that the AND gate did on the way up.
Then try the A narrow glitch preset in either polarity. A single-slot spike on the input produces a pulse just as respectable as the one a proper clock cycle produces. A pulse detector cannot tell the difference between a clock edge and interference, and neither can the flip-flop behind it. That is why clock lines get more care in a layout than anything else on the board, and it is worth remembering the first time a circuit counts to seven when it was asked to count to five.
Step 5: Put the pulse in front of a latch
Section titled “Step 5: Put the pulse in front of a latch”Open SR flip-flop. Set S to 1 and watch nothing happen. Then press Clock up and use Step four times.
Step one is the edge producing the pulse. Step two is the pulse opening the two steering gates, which is exactly what the enable did on the gated latch. Step three is the latch resolving, in the same three moves as before: one NOR gate forced from outside, the other following from the feedback, and a check that going round again changes nothing. Step four is the pulse ending and the steering gates going back to 0, which is the hold case.
Now do the thing that shows what has been gained. With the clock still high, change S and R as much as you like.
Nothing moves, and you can see why rather than take it on trust. The clock pin reads 1, the S pin reads 1, and the detector still says it is waiting for an edge, so P is 0 and both steering gates are producing 0 no matter what arrives at their other input. The clock is high, which on a gated latch would have meant wide open, and here means nothing at all. The flip-flop stopped listening a few nanoseconds after the edge and will not listen again until the clock has gone down and come back up. Being level sensitive and being edge triggered are genuinely different behaviours, and the drawing is the same circuit with one block added.
Step 6: Notice what has not been fixed
Section titled “Step 6: Notice what has not been fixed”Set both S and R to 1 and clock it.
At step three both outputs go to 0, exactly as they did on the bare latch, because both NOR gates are being forced from outside and neither needs the feedback. Take the fourth step and the outputs go to unknown.
That last transition is the honest answer rather than a refusal to compute. When the pulse ends, both steering gates go back to 0 at the same moment and both NOR gates are released together, so the pair settles according to which gate happens to be a little faster. On one part it will be one way, on the next part it may be the other, and no amount of care in the design will change it.
A clock says when a circuit listens. It has nothing to say about what it is being told, and the combination that was not allowed is still not allowed.
Step 7: The one you will actually use
Section titled “Step 7: The one you will actually use”Open D flip-flop and look at the timing diagram before touching the controls.
Two Q traces are drawn. The upper one is the flip-flop, and the lower one is a plain D latch given the same D and the same clock. Compare them. The latch follows D wherever the clock is high, so its trace moves in the middle of a clock cycle as readily as at the start of one. The flip-flop changes only at the arrows and is flat everywhere else.
Now try the D wobbling between edges preset. The latch output becomes almost meaningless, changing whenever D does. The flip-flop output changes only at the arrows, and between them it holds one value that can be read at any moment. That is the whole reason a system with a shared clock works: every stored value is guaranteed to be steady except at the instants everybody has agreed on.
The A glitch that misses the edge preset makes the same point from the other side. A spike on D that lands between two edges is simply not seen. Land one on an edge and it is stored as faithfully as anything else.
Step 8: Setup, hold and the small print
Section titled “Step 8: Setup, hold and the small print”The window is narrow but it is not zero, and D has to be steady across it.
The amber sliver drawn before each arrow is the setup time: the interval before the edge in which the data must already have settled. There is a matching hold time after the edge in which it must not yet move. Violate either and the flip-flop may take neither 0 nor 1 but sit part way between them for a while before falling to one or the other, which is called metastability. It is not a rare theoretical curiosity: it is the reason every data sheet quotes those two numbers, and the reason a signal arriving from outside the system, which knows nothing about your clock, has to be passed through two flip-flops in series before it can be trusted.
Step 9: Make the forbidden combination do something useful
Section titled “Step 9: Make the forbidden combination do something useful”Open JK flip-flop, set J and K both to 1, and clock it repeatedly.
The output changes over at every edge. Do it four or five times and then look at the Toggle throughout preset on the timing diagram, where Q completes one cycle for every two clock cycles. A JK with both inputs high divides the clock frequency by two, and a row of them divides by four, eight and sixteen, which is a counter.
The mechanism is in the drawing rather than in the truth table, and with J and K both at 1 you can read it off the levels. One of the two three-input gates is producing 1 and the other 0, and the only input they disagree on is the one that came from the outputs. Step the flip-flop through an edge, then do it again, and watch which gate produces the 1 change over each time.
Each steering gate needs three things at once. The reset gate needs the pulse, and K, and Q itself, so it can only fire if the flip-flop is currently set. The set gate needs the pulse, and J, and the complement of Q, so it can only fire if the flip-flop is currently clear. Exactly one of Q and its complement is ever high, so the two gates can never be asserted together, and the combination that produced a race on the SR flip-flop now produces a well-defined change of state. The fault was not designed around; it was designed out, in the same way the D latch removed the fault from the gated SR latch, and again it cost one wire rather than a rule in the documentation.
There is a condition attached, and it is the reason the narrow pulse matters more here than anywhere else. The state that picks the gate is the state before the change. If the pulse lasted long enough for the new value to travel round the feedback while the gates were still open, the flip-flop would toggle again, and again, for as long as the window stayed open, and the state it finished in would be a matter of luck. That failure is called the race-around condition, and the whole first tab exists to prevent it.
Notice also that this tab starts cleared rather than unknown, with Clear and Preset buttons where the other tabs have Forget the state. A JK works out what to do by reading its own outputs, so a JK that has never been in a state cannot work out what to do with J and K both high. Real parts solve this with asynchronous preset and clear pins that force the latch directly, without waiting for a clock, and one of the first things you do on power-up is use them.
Check your understanding
Section titled “Check your understanding”What sets the width of the pulse produced by an edge detector?
A positive-edge-triggered D flip-flop has its clock sitting high. D changes from 0 to 1 and stays there. What does Q do?
Match each part or idea to what it actually does
Why can a JK flip-flop never have both of its steering gates asserted at the same time?
A JK flip-flop is built with a pulse detector whose pulse is made much wider, wide enough for a change on Q to travel back round the feedback while the pulse is still high. What goes wrong?
Wrap-up
Section titled “Wrap-up”Five things to take from this.
- Propagation delay, which has been an obstacle in every circuit up to now, is the mechanism here. A pulse detector produces a window whose width is a property of the silicon rather than of anything you control, and that is precisely why it is short enough to be useful.
- Level triggered and edge triggered are different behaviours, not different words for the same thing. A latch listens while its enable is high; a flip-flop listens for a few gate delays after an edge and is deaf the rest of the time, including while the clock is still high.
- Putting a clock in front of a circuit controls when it listens and says nothing about what it is told. The SR flip-flop has exactly the same forbidden combination as the SR latch, for exactly the same reason.
- The D flip-flop is the workhorse. Its output is steady except at the instants everybody has agreed on, which is what allows a system full of them to share one clock and read each other’s outputs without interfering.
- The JK converts the forbidden combination into a toggle by feeding the outputs back into the steering gates, and it works only because the window is narrower than the loop it feeds.
Both problems the latch demonstration left open have now been dealt with. A flip-flop cannot be asked for anything contradictory, and its output does not move while anything is reading it.
What that makes possible is the whole of the rest of the subject. A row of D flip-flops sharing one clock is a register, which stores a number rather than a bit. A JK with both inputs high divides a frequency by two, and several of them in a row count. Once every stored value in a system changes only at the same agreed instants, you can reason about what the system will do next, and the next demonstration is about doing exactly that.
© 2026 Derek Molloy, Dublin City University. All rights reserved.